Fin field-effect transistor (FinFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. A FinFET device can be built on a semiconductor substrate, where a semiconductor material, such as silicon, is patterned into fin-like shapes and functions as the channels of the transistors.
Known FinFET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to a substrate) between source/drain regions at opposite ends of the fins in the horizontal direction. The known structures have their architectures limited by scaling plateaus. For example, known horizontal devices can have contacted poly pitch (CPP) plateaus between 30 nm and 50 nm, and are driven by such competing considerations as electrostatics, contact resistance (Rcontact), and maximum voltage (Vmax). As horizontal devices are scaled down, there is reduced space for metal gate and source/drain contacts, which leads to degraded short-channel control and increased middle of the line (MOL) resistance (e.g., ˜15% Ieff drop due to MOL resistance for a 7 nm FinFET).
Vertical transport architecture FET devices include source/drain regions at ends of the fins on top and bottom sides of the fins so that current runs through the fins in a vertical direction (e.g., perpendicular to a substrate) from a bottom source/drain region to a top source/drain region. Vertical transport architecture devices are designed to extend the product value proposition beyond conventional plateaus and address the limitations of horizontal device architectures by, for example, decoupling of gate length from the contact gate pitch, providing a FinFET-equivalent density at a larger CPP, and providing lower MOL resistance. Therefore, vertical transistors have been explored as a viable device option for continued complementary metal-oxide semiconductor (CMOS) scaling beyond 7 nm node and are promising for beyond 5 nm technology.